1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to silicon junction devices formed in silicon on insulator (SOI) technology.
2. Background Description
Typical prior art bulk silicon such as diodes, field effect transistors (FETs) and bipolar transistors formed on a silicon wafer are subject to parasitic effects resulting from other bulk devices in close proximity and from vertical structural asymmetry. These parasitic effects include voltage limitations and cross-device interference.
Consequently, typical bulk semiconductor processes, especially FET processes that include both p-type FETs (PFETs) and n-type FETS (NFETs) and commonly referred to as CMOS, require dedicated structures to localize and reduce parasitic effects. These specialized structures include providing surface diffusions referred to as guard rings, individual doped wells (N-wells and/or P-wells) and including a buried insulator.
Discrete devices, i.e., individually formed and packaged transistors or diodes, are normally free from these parasitic effects. One example of such discrete device is a discrete JFET. A discrete JFET may be formed in a doped silicon bar by forming contacts at opposite ends of the bar and a diffusion ring of an opposite dopant type therebetween. However, these discrete devices have limited applications and do not have any of the advantages of monolithic circuit integration.
Thus, there is a need for individually isolated semiconductor devices that may be integrated into a single circuit on a single chip.